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CXB1577Q
Post-Amplifier for Optical Fiber Communication Receiver
Description The CXB1577Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is equipped with the signal detection function, which is used to enable TTL/ECL outputs. Also, the output disable function performs the output shutdown. 3.3V/5.0V can be used for the supply voltage. Features * Output disable function (TTL input) * Signal detection function (TTL/ECL output) * Supply voltage supports both 3.3V/5.0V Applications * SONET/SDH: * Fibre Channel: : * Gigabit-Ethernet: 40 pin QFP (Plastic)
622.08Mbps 531.25Mbps 1.062Gbps 1.25Gbps
Absolute maximum Ratings * Supply voltage * Storage temperature * Input voltage difference VD - VD * SW input voltage * ECL output current * TTL output current (High level) * TTL output current (Low level) --
VCC - VEE Tstg Vdif Vi IOQ/SD-ECL IOH SD-TTL IOL SD-TTL
-0.3 to +7 -65 to +150 0 to +2 VEE to VCC -30 to 0 -20 to 0 0 to 20
V C V V mA mA mA
Recommended Operating Conditions * Supply voltage * Termination voltage (for data) * Termination voltage (for alarm 1,alarm 2) * Termination resistance (for data) * Termination resistance (for alarm 1) * Termination resistance (for alarm 2) * Operating temperature Structure Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--
VCC - VEE VCC - VTD VTA RTD RTA1 RTA2 Ta
3.3 0.2/5 0.25 1.8 to 2.2 VEE 46 to 56 240 to 300 460 to 560 -40 to +85
V V V C
-1-
E96Z24-PS
CXB1577Q
Block Diagram and Pin Configuration
CAP3
CAP2
VEE4
VEE2
N.C.
VC3
VEEI
DN
30
29
28
27
26
25
24
23
UP
22
21
VCC4 31
N.C.
20 VCC2
VC1 32
V
19
VEE1
SD-TTL 33 peak hold SDB-TTL 34 peak hold
18 D
17
DB
SD-ECL 35
16
CAP1
SDB-ECL 36
15
CAP1B
Q 37
14
N.C.
QB 38
13
VC0
VCC3 39
12
VCC1
N.C. 40
11 TM
1
2
3
4
5
6
7
8
9
10
VEE3
VCC2
ODIS
-2-
VEE2
VEE1
N.C.
VC2
N.C.
N.C.
SW
CXB1577Q
Pin Description Pin No. 1 Typical pin voltage DC VEE3
-3.3V / -5V
Symbol
Equivalent circuit
Description Negative power supply for ECL output buffer.
VCC2
AC
0V
(Open)
10k 2 300 10k VREF
2
ODIS
or
-3.3V / -5V
Controls the output shutdown function. High voltage when open; the Q output is fixed to Low. Low voltage when connected to VEE; the D input results in the Q output with ECL level. TTL level is also available.
VEE2
VCC2
0V
(Open)
60k 3 40k
3
SW
or
-3.3V / -5V
Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 40mVp-p. Low voltage when connected to VEE; the amplitude becomes 20mVp-p.
VEE2
4
VCC2
0V
Positive power supply for digital block.
VCC2 6k
0V 5 VC2
/-1.7V
5 2k
(Open)
VEE2
Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE.
6 7 8 9 10 VEE2 VEE1
-3.3V / -5V -3.3V / -5V
N.C.
No connected.
Negative power supply for digital block. Negative power supply for analog block.
10 11
11
TM
-1.8V / -3.5V
Chip temperature monitor.
VEE1
-3-
CXB1577Q
Pin No. 12
Symbol VCC1
Typical pin voltage DC 0V AC
Equivalent circuit
Description Positive power supply for analog block.
VCC3 6k
13
VC0
0V /-1.7V (Open)
13 2k
Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE.
VEE3
14 15 16
N.C. CAP1B
VCC1
No connected.
CAP1 -0.9V to -1.3V -1.7V -0.9V to -1.3V -1.7V -3.3V /-5V 0V
18 17 1k 1k 7.5k 7.5k 200 16 100p 15 200
17
DB
Pins 15 and 16 connect a capacitor which determines the cut-off frequency for DC feedback block. Pins 17 and 18 are input pins for limiting amplifier block. Input the signal with AC coupled.
18
D
VEE1
19 20 21 22
VEE1 VCC2 N.C. UP
Negative power supply for analog block. Positive power supply for digital block. No connected. Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor by shorting the VEEI pin to VEE. Generates the default voltage between UP and DOWN. The voltage (8.0mV for input conversion) can be generated between UP and DOWN (Pins 22 and 23) as alarm setting level by connecting this pin to VEE. Negative power supply for digital block.
VCC2 986 140.9 140.9 22 100 23 100 VCS SW SW VEE2 24
23
DN
24
VEEI
-3.3V /-5V
25
VEE2
-3.3V /-5V
-4-
CXB1577Q
Pin No.
Symbol
Typical pin voltage DC AC
Equivalent circuit
Description
26 80 10p
VCC2
26
CAP2
-1.8V
5A
200
VEE2
27 80 10p
VCC2
Connects a peak hold circuit capacitor for alarm block. 470pF should be connected to Vcc each. CAP2 pin connects a peak hold capacitor for alarm level setting block. CAP3 pin connects a peak hold capacitor for limiting amplifier signal.
27
CAP3
-1.8V
5A
200
VEE2
VCC3 6k
28
VC3
0V /-1.7V
(Open)
28 2k
Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE.
VEE3
29 30 31
VEE4 N.C. VCC4
-3.3V /-5V
Negative power supply for TTL output buffer. No connected.
0V
Positive power supply for TTL output buffer.
VCC3 6k
0V 32 VC1
-1.7V
32 2k
(Open)
VEE3
Switches 3.3V/5V. Short this pin to Vcc for 3.3V between Vcc and VEE. Leave this pin open for 5V between Vcc and VEE.
-5-
CXB1577Q
Pin No.
Symbol
Typical pin voltage DC AC
Equivalent circuit
Description
VCC4
33
SD-TTL
VEE or VEE + 3V
40k
33
Alarm signal TTL level output.
VEE4
VCC4
34
SDB-TTL
VEE or VEE + 3V
40k
34
Alarm signal TTL level output.
VEE4
35
SD-ECL
-0.9V or -1.7V
VCC3
35 36
Alarm signal ECL level output. Terminate this pin in 510 to VEE at VEE = 5V; in 270 to VEE at VEE = 3.3V.
36
SDB-ECL
-0.9V or -1.7V
VEE3
-6-
CXB1577Q
Pin No.
Symbol
Typical pin voltage DC AC
Equivalent circuit
Description
37
Q
-0.9V or -1.7V
VCC3
37 38
Data signal output. Terminates this pin in 50 to VTT = Vcc-2V.
38
QB
-0.9V or -1.7V
VEE3
39 40
VCC3 N.C.
0V
Positive power supply for ECL output buffer. No connected.
-7-
CXB1577Q
Electrical Characteristics DC Characteristics Item Supply current Q/QB High output voltage Q/QB Low output voltage VCC = GND, VEE = -5V 5%, Ta = -40 to +85C, VC0 to VC3 = open, or VCC = GND, VEE = -3.3V 5%, Ta = -40 to +85C, VC0 to VC3 = GND Symbol IEE VOH VOL 50 to VTT Ta = 0 to +85C When Vcc - VEE = 5.0V, 510 to VEE; when Vcc - VEE = 3.3V, 270 to VEE Ta = 0 to +85C Conditions Min. -74 -1100 -1860 -1100 Typ. -51 Max. -34 -860 -1620 -860 mV Unit mA
SD-ECL/SDB-ECL High output voltage VOH-E SD-ECL/SDB-ECL Low output voltage VOL-E
-1890
-1650
IOH = -0.4mA, SD-TTL/SDB-TTL High output voltage 1 VOH-T1 VCC - VEE = 3.3V, Ta = 0 to +85C IOH = -0.4mA, SD-TTL/SDB-TTL High output voltage 2 VOH-T2 VCC - VEE = 5V, Ta = 0 to +85C SD-TTL/SDB-TTL Low output voltage SW High input voltage SW Low input voltage SW High input current SW Low input current ODIS High input voltage ODIS Low input voltage ODIS High input current ODIS Low input current D/DB input resistance VOL-T VIHSW VILSW IIHSW IILSW VIHOD VILOD IIHOD IILOD Rin IOL = 2mA Ta = 0 to +85C
VEE + 2.2
VEE + 2.4 V VEE + 0.5 VCC VEE + 0.5 10 -100 A
at SW pin Open: High VCC - 0.5 VEE
at ODIS pin Open: High VEE + 2.0 VEE
VCC + 0.5 VEE + 0.8 20
V
-400 765 1020 1275
A
-8-
CXB1577Q
AC Characteristics
VCC = GND, VEE = -5V 5%, Ta = -40 to +85C, VC0 to VC3 = open, or VCC = GND, VEE = -3.3V 5%, Ta = -40 to +85C, VC0 to VC3 = GND Symbol Vmax Conditions single-ended input Min. 1600 52 SW pad: Low, single-ended input 20 mVp-p 40 3 3 6 6 7 dB 7 Typ. Max. Unit mVp-p dB
Item Maximum input voltage amplitude
Amplifier gain (excluding the output buffer) GL Identification maximum voltage amplitude of alarm level VmaxA1
SW pad: Open High, VmaxA2 single-ended input P1 SW pin: Low, at default alarm level SW pin: Open High, at default alarm level UP/DOWN pin: open, VEEI = VEE, Differential voltage input 20% to 80% 50 to VTT VEE + 0.8V to VEE + 2.0V CL = 10pF 20% to 80% When Vcc - VEE = 5.0V, 510 to VEE, when Vcc - VEE = 3.3V, 270 to VEE
SD/SDB hysteresis width
P2
Alarm setting level for default Q/QB rise time Q/QB fall time SD-TTL/SDB-TTL rise time SD-TTL/SDB-TTL fall time SD-ECL/SDB-ECL rise time
Vdef TrQ TfQ TrSDT TfSDT TrSDE TfSDE TPD Tas Tdas Tasd Tdasd
7.0
8.4 230 230
9.7 350 350 10 10 1.6 1.6
mV
ps
ns
SD-ECL/SDB-ECL fall time Propagation delay time SD response assert time SD response deassert time SD response assert time for alarm level default SD response deassert time for alarm level default
0.4 1 2 3 4 0 2.3 0 2.3
1.9 100 100 100 100 s
1 VUP - VDOWN = 100mV, Vin = 100mVp-p (single ended), SW pin: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, connect VEEI to VEE. 2 VUP - VDOWN = 100mV, Vin = 1Vp-p (single ended), SW pin: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, connect VEEI to VEE. 3 Vin = 50mVp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect VEEI to VEE. 4 Vin = 1Vp-p (single ended), SW pin: Low, peak hold capacitance of 470pF, connect VEEI to VEE.
-9-
CXB1577Q
DC Electrical Characteristics Measurement Circuit
C3
C3
CAP3
CAP2
N.C.
VEE4
VEE2
VC3
VEEI
DN
30
29
28
27
26
25
24
23
UP
22
21
N.C.
VCC4 31 VC1 32 SD-TTL 33 peak hold SDB-TTL 34 SD-ECL 510 270 510 270 51 QB 51 VTT -2V VCC3 39 12 38 13 SDB-ECL 36 Q 37 14 15 35 16 peak hold 18 V 19 20
VCC2
VEE1 C1 VD D C1 DB 17 CAP1
CAP1B
C2
N.C. VC0
VCC1
TM N.C. 40 11
1
2
3
4
5
6
7
8
9
10
VCC2
VEE3
ODIS
N.C.
N.C.
N.C.
VEE2
VEE1
SW
VC2
VODIS
VSW
VEE -5.0V/-3.3V
When VEE = -5.0V: VC0 to VC3 = open When VEE = -3.3V: VC0 to VC3 = Vcc
- 10 -
CXB1577Q
AC Electrical Characteristics Measurement Circuit
470p
470p
REX1
N.C.
CAP3
CAP2
VEE4
VC3
VEE2
VEEI
DN
30
29
28
27
26
25
24
23
UP
22
21
VCC4 31 VC1 32 SD-TTL 33 Oscilloscope Hi-Z input peak hold SDB-TTL 34 SD-ECL Z0 = 50 SDB-ECL Z0 = 50 Oscilloscope 50 input Z0 = 50 QB Z0 = 50 VCC3 39 12 38 13 Q 37 36 15 35 16 peak hold 18 V 19 20
N.C.
VCC2
VEE1 0.047F
D
DB 17 CAP1 1F
0.047F
CAP1B
14 N.C. VC0
VCC1
TM N.C. 40 11
1
2
3
4
5
6
7
8
9
10
ODIS
VEE2
SW
VC2
VCC2
VEE3
N.C.
N.C.
VCC +2V
VEE -3V/ -1.3V
When VEE = -3.0V: VC0 to VC3 = open When VEE = -1.3V: VC0 to VC3 = Vcc
- 11 -
N.C.
VEE1
CXB1577Q
Application Circuit
VEE 470p 470p REX1
VC3
VEE2
N.C.
CAP3
VEE4
CAP2
VEEI
DN
30
29
28
27
26
25
24
23
UP
22
21
VCC4 31
N.C.
20 VCC2 Signal Generator 51 VIN
VC1 32 SD-TTL 33 TTL Output peak hold SDB-TTL 34 SD-ECL 35 ECL Output SDB-ECL 36 51 ECL Output 51 VTT -2.0V QB 38 Q 37 peak hold
V
19
VEE1 VTT D
51 0.047F
18 DB 17 CAP1 16 CAP1B 15 1F VTT 51 VTT 0.047F 51
14
N.C.
13
VC0
VCC3 39
12
VCC1
N.C. 40
11 TM
1
2
3
4
5
6
7
8
9
10
ODIS
SW
VEE2
N.C.
N.C.
VC2
TTL Input When VEE = -3.3V: VC0 to VC3 = Vcc When VEE = -5.0V: VC0 to VC3 = open
VEE
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
VCC2
VEE3
- 12 -
VEE1
N.C.
CXB1577Q
Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 17 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1k f2: 3.4kHz C1 (external): 0.047F C2 (external): 1F R2 (internal): 7.5k f1: 21Hz
D C1
18 To IC interior 17 C1 R1 R1
R2 16 C2 15 R2
Fig. 1
Feedback frequency response
Amplifier frequency response
Gain
f1
f2
Frequency
Fig. 2
- 13 -
CXB1577Q
2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 22 and 23 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to connect Pin 24 to VEE and leave Pins 22 and 23 open to set an alarm level default value (8mV for input conversion). The other is to connect Pin 24 to VEE and set a desired alarm level using the external resistors REX1, REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 22 and 23 or connect REX3 between Pin 23 and Vcc when less alarm level is desired to be set than its default value; connect REX2 between Pin 22 and Vcc when more alarm level is desired to be set than its default value. However, the Pin 22 voltage must be higher than that of Pin 23. This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to 40mVp-p when Pin 3 is left open (High level) and it is set to 20mVp-p when Pin 3 is Low level. Therefore, the noise margin can be increased by setting Pin 3 to Low level when the small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 5. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. This IC is designed to externally have the capacitor C3, and the C3 value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 6. REX1: 100 (when the alarm level is set to 4mV for input conversion.) REX2: 8k (when the alarm level is set to 10mV for input conversion.) REX3: 4k (when the alarm level is set to 4mV for input conversion.) C3: 470pF The table below shows the alarm logic. Optical signal input state Signal input Signal interruption SD High level Low level SD Low level High level The table below shows the output disable function logic. Optical signal input state ODIS: Open High ODIS: Low Q Fixed Low Data Q Fixed High Data
Ra1, Ra2A and Ra2B values are typical values. VCCA Ra1 986 Ra2A 141 Ra2B 141
From limiting amplifier
Peak Hold
SD-TTL SDB-TTL
Peak Hold
SD-ECL SDB-ECL
VCCA VCS V 3 IC interior 22 23 24 24 22 23 26 27 10p 10p
VCCA
VEEI
UP
DN
IC exterior
REX2 VEE
REX1
C3 REX3 VCC VCC
C3
VCC
VCC
Fig. 3 - 14 -
CXB1577Q
VDAS Deassert level VAS Assert level High level
SD output
Peak hold output voltage
Low level
SW Low
VDAS Small 3dB 3dB Alarm setting input level Hysteresis Input electrical signal amplitude
VAS Large
SW Open High
0
20
40 Input voltage [mVp-p]
Fig. 4
Fig. 5
Data input (D)
Hysteresis width
Alarm setting level
Data output (Q)
Alarm output (SD)
Assert time
Deassert time
Fig. 6
- 15 -
CXB1577Q
Example of Representative Characteristics 1. Q/QB output waveform
Q
VCC = GND VEE = -3.3V VTT = -2V Ta = 27C D = 622Mbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50 to VTT
QB
Ch. 1 = 400mV/div OFFSET = -1330mV, Ch. 2 = 400mV/div OFFSET = -1330mV, Timebase = 500ps/div
Fig. 7
Q
VCC = GND VEE = -3.3V VTT = -2V Ta = 27C D = 622Mbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50 to VTT
QB
Ch. 1 = 400mV/div OFFSET = -1330mV, Ch. 2 = 400mV/div OFFSET = -1330mV, Timebase = 500ps/div
Fig. 8
Q
VCC = GND VEE = -3.3V VTT = -2V Ta = 27C D = 1.25Gbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50 to VTT
QB
Ch. 1 = 400mV/div OFFSET = -1330mV, Ch. 2 = 400mV/div OFFSET = -1330mV, Timebase = 200ps/div
Fig. 9 - 16 -
CXB1577Q
Q
VCC = GND VEE = -3.3V VTT = -2V Ta = 27C D = 1.25Gbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50 to VTT
QB
Ch. 1 = 400mV/div OFFSET = -1330mV, Ch. 2 = 400mV/div OFFSET = -1330mV, Timebase = 200ps/div
Fig. 10 2. Bit error rate
Bit error rate vs. Data input level
10 -3 10
-4
622Mbps 1.0Gbps 1.25Gbps VCC = GND VEE = -3.3V VTT = -2V Ta = 27C Single input pattern: PRBS223-1 Q/QB = 50 to VTT
10 -5
Bit error rate
10 -6 10 -7 10 -8 10 -9 10 -10 1.5 2 2.5 3 3.5 Data input level [mVp-p]
4
4.5
3. Alarm level
Alarm level vs. REX1
9 8 7 SW = H SW = L
Fig. 11
Alarm level temperature
6.0 5.5 5.0 SW = H SW = L
Alarm level [mV]
Alarm level [mV]
fin = 100Mbps VCC - VEE = 3.3V Ta = 27C Differential input 103 UP-DOWN (REX1) [] 104
4.5 4.0 3.5 3.0 2.5 2.0 -40 -20 0 40 20 Ta [C] 60 80 fin = 100Mbps VCC - VEE = 3.3V Up-Down = 200 (REX1)
6 5 4 3 2 102
Fig. 12 - 17 -
Fig. 13
CXB1577Q
Alarm level supply voltage
6.0 5.5 5.0 SW = H SW = L 16 15 14
Alarm level vs. REX2
fin = 100Mbps VCC - VEE = 3.3V Ta = 27C Differential input
Alarm level [mV]
Alarm level [mV]
fin = 100Mbps Ta = 27C Up-Down = 200 (REX1) 3.1 3.2 3.4 3.3 VCC - VEE [V] 3.5 3.6
4.5 4.0 3.5 3.0 2.5 2.0 3.0
13 12 11 10 9 8 103 SW = H SW = L 104 VCC-UP (REX2) [] 105
Fig. 14
Alarm level temperature
15.0 14.5 14.0 SW = H SW = L 15.0 14.5 14.0 SW = H SW = L
Fig. 15
Alarm level supply voltage
Alarm level [mV]
13.5 13.0 12.5 12.0 11.5 11.0 -40 -20 0 40 20 Ta [C] 60 80 fin = 100Mbps VCC - VEE = 3.3V VCC-UP = 5k (REX2)
Alarm level [mV]
13.5 12.0 12.5 12.0 11.5 11.0 3.0 fin = 100Mbps Ta = 27C VCC-UP = 5k (REX2) 3.1 3.2 3.4 3.3 VCC - VEE [V] 3.5 3.6
Fig. 16
Alarm level vs. REX3
9 SW = H SW = L 8 6.0 5.5 5.0 SW = H SW = L
Fig. 17
Alarm level temperature
fin = 100Mbps VCC - VEE = 3.3V VCC-Down = 3k (REX3)
Alarm level [mV]
Alarm level [mV]
fin = 100Mbps VCC - VEE = 3.3V Ta = 27C Differential input 104 VCC-DOWN (REX3) [] 105
7
4.5 4.0 3.5 3.0 2.5 -40 -20 0 20 Ta [C] 40 60 80
6
5
4
3 103
Fig. 18 - 18 -
Fig. 19
CXB1577Q
Alarm level supply voltage
6.0 5.5 5.0 SW = H SW = L fin = 100Mbps Ta = 27C VCC-Down = 3k (REX3) 8.0 7.0 6.0 5.0
Hysteresis width vs. Alarm level
SW = H SW = L
Alarm level [mV]
4.5 4.0 3.5 3.0 2.5 2.0 3.0 3.1 3.3 3.2 3.4 VCC - VEE [V] 3.5 3.6
HYS [dB]
4.0 3.0 2.0 1.0 0.0 2.0 fin = 100Mbps VCC - VEE = 3.3V Ta = 27C 4.0 6.0 10.0 8.0 Alarm level [mV] 12.0 14.0
Fig. 20
Hysteresis width temperature
8.0 7.0 6.0 5.0 SW = H SW = L 8.0 7.0 6.0 5.0 SW = H SW = L
Fig. 21
Hyteresis width supply voltage
HYS [dB]
HYS [dB]
fin = 100Mbps VCC - VEE = 3.3V Up, Down = Open VEEI = VEE -40 -20 0 20 40 Ta [C] 60 80
4.0 3.0 2.0 1.0 0.0
4.0 3.0 2.0 1.0 0.0 3.0 fin = 100Mbps Ta = 27C Up, Down = Open VEEI = VEE 3.1 3.3 3.2 3.4 VCC - VEE [V] 3.5 3.6
Fig. 22
Alarm level vs. Data rate
16 14 12 SW = H SW = L 10 12 SW = H SW = L
Fig. 23
Hysteresis width vs. Data rate
Alarm level [mV]
8 10 8 6 4 2 0 200 400 600 800 fin [Mbps] 1000 1200 1400 VCC - VEE = 3.3V Ta = 27C Up, Down = Open VEEI = VEE 2 VCC - VEE = 3.3V Ta = 27C Up, Down = Open VEEI = VEE 0 200 400 600 800 fin [Mbps] 1000 1200 1400
HYS [dB]
6
4
0
Fig. 24 - 19 -
Fig. 25
CXB1577Q
4. DC voltage
SD-ECL "H" level supply voltage
-860 SD-ECL SDB-ECL -900 Ta = 27C -900 -860 SD-ECL SDB-ECL VCC - VEE = 3.3V
SD-ECL "H" level temperature
"H" level [mV]
-980
"H" level [mV]
3.0 3.3 3.2 3.4 VCC - VEE [V] 3.6
-940
-940
-980
-1020
-1020
-1060
-1060
-1100 3.1 3.5
-1100 -50
0 Ta [C]
50
100
Fig. 26
SD-ECL "L" level supply voltage
SD-ECL SDB-ECL Ta = 27C -1680
Fig. 27
SD-ECL "L" level temperature
SD-ECL SDB-ECL VCC - VEE = 3.3V
-1680
-1720
-1720
"L" level [mV]
-1760
"L" level [mV]
-1760
-1800
-1800
-1840
-1840
-1880 3.0 3.1 3.3 3.2 3.4 VCC - VEE [V] 3.5 3.6
-1880 -50
0 Ta [C]
50
100
Fig. 28
SD-TTL "H" level supply voltage
3.4 Ta = 27C 3.2 3.2 3.4
Fig. 29
SD-TTL "H" level temperature
VCC - VEE = 3.3V
3.0
3.0
"H" level [V]
2.8
"H" level [V]
3.1 3.2 3.4 3.3 VCC - VEE [V] 3.5 3.6
2.8
2.6
2.6
2.4
2.4
2.2 3.0
2.2 -50
0 Ta [C]
50
100
Fig. 30 - 20 -
Fig. 31
CXB1577Q
SD-TTL "L" level supply voltage
400 Ta = 27C 400
SD-TTL "L" level temperature
VCC - VEE = 3.3V
350
350
"L" level [mV]
300
"L" level [mV]
3.0 3.3 3.2 3.4 VCC - VEE [V] 3.6
300
250
250
200 3.1 3.5
200 -50
0 Ta [C]
50
100
Fig. 32
Q "H" level supply voltage
-860 Q-H QB-H -900 Ta = 27C -900 -860 Q-H QB-H
Fig. 33
Q "H" level temperature
VCC - VEE = 3.3V
"H" level [mV]
-980
"H" level [mV]
-940
-940
-980
-1020
-1020
-1060
-1060
-1100 3.0 3.1 3.3 3.2 3.4 VCC - VEE [V] 3.5 3.6
-1100 -50
0 Ta [C]
50
100
Fig. 34
Q "L" level supply voltage
-1620 Q-L QB-L -1660 Ta = 27C -1660 -1620 Q-L QB-L
Fig. 35
Q "L" level temperature
VCC - VEE = 3.3V
-1700
-1700
"L" level [mV]
-1740
"L" level [mV]
3.0 3.3 3.2 3.4 VCC - VEE [V] 3.6
-1740
-1780
-1780
-1820
-1820
-1860 3.1 3.5
-1860 -50
0 Ta [C]
50
100
Fig. 36 - 21 -
Fig. 37
CXB1577Q
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
9.0 0.4 + 0.4 7.0 - 0.1 30 21
+ 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1
31
20
A
40 1 0.65 + 0.15 0.3 - 0.1 + 0.15 0.1 - 0.1
11
10 0.12 M
0.5 0.2
(8.0)
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.2g
DETAIL A SONY CODE EIAJ CODE JEDEC CODE QFP-40P-L01 QFP040-P-0707
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 22 -

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